A Non-Binary Parallel Arithmetic Architecture

Document Type

Conference Proceeding

Department or Administrative Unit

Computer Science

Publication Date

5-1-2000

Abstract

In this paper we present a novel parallel arithmetic architecture using an efficient non-binary logic scheme. We show that by using parallel broadcasting (or domino propagating) state signals, on short reconfigurable buses equipped with a type of switches, called GP (generate-propagate) shift switches, several arithmetic operations can be carried out efficiently. We extend a recently proposed shift switching mechanism by letting the switch array automatically generate a semaphore to indicate the end of each domino process. This reduces the complexity of the architecture and improves the performance significantly.

Comments

This article was originally published in IPDPS 2000: Parallel and Distributed Processing. The full-text article from the publisher can be found here.

Due to copyright restrictions, this article is not available for free download from ScholarWorks @ CWU.

Journal

Parallel and Distributed Processing. IPDPS 2000

Rights

© Springer-Verlag Berlin Heidelberg 2000

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