A Non-Binary Parallel Arithmetic Architecture
Department or Administrative Unit
Computer Science
Document Type
Conference Proceeding
Author Copyright
© Springer-Verlag Berlin Heidelberg 2000
Publication Date
5-1-2000
Journal
Parallel and Distributed Processing. IPDPS 2000
Abstract
In this paper we present a novel parallel arithmetic architecture using an efficient non-binary logic scheme. We show that by using parallel broadcasting (or domino propagating) state signals, on short reconfigurable buses equipped with a type of switches, called GP (generate-propagate) shift switches, several arithmetic operations can be carried out efficiently. We extend a recently proposed shift switching mechanism by letting the switch array automatically generate a semaphore to indicate the end of each domino process. This reduces the complexity of the architecture and improves the performance significantly.
Recommended Citation
Lin R., Schwing J.L. (2000) A Non-Binary Parallel Arithmetic Architecture. In: Rolim J. (eds) Parallel and Distributed Processing. IPDPS 2000. Lecture Notes in Computer Science, vol 1800. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45591-4_19
Comments
This article was originally published in IPDPS 2000: Parallel and Distributed Processing. The full-text article from the publisher can be found here.
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